Integration of Error-Tolerant Flip-Flops in an Iterative ASIC Design Flow
EECSE6693 VLSI Design Project · Columbia University · 2025
Conventional ASIC design relies on conservative timing margins to guarantee functionality for every chip produced across all possible process, voltage, and temperature (PVT) corners. Timing closure ends up driven by a small subset of worst-case paths that are rarely exercised under typical conditions, and since dynamic power scales quadratically with supply voltage, the extra guardband translates directly into wasted energy. This project explores reclaiming that performance and energy by allowing controlled timing violations, using error-tolerant, time-borrowing flip-flops (ETFFs) integrated into an industry-standard Cadence design flow.
Error-Tolerant Flip-Flops
The ETFF is a soft-edge, time-borrowing flip-flop: its slave latch is clocked slightly later than its master latch, creating a short transparency window after the clock edge. A signal that arrives slightly late still propagates correctly, borrowing time from the next logic stage, while an error flag is raised if the late value differs from the one sampled at the edge. Unlike detection-and-correction schemes such as Razor, no instruction replay or pipeline flush is needed; the error is masked.
Monitoring these late signals enables performance tuning: no errors means the chip can run faster or at lower supply voltage, while an error every ~10,000 cycles indicates the chip is operating at its point of first failure (PoFF), the true performance limit of that individual die rather than the worst-case design corner.
Iterative Integration Flow
Rather than proposing a new flip-flop circuit, the project focused on realistically integrating ETFFs into the Cadence Genus/Innovus flow, iterating:
- Baseline synthesis and place-and-route run with no ETFFs
- Identify the N lowest-slack register-to-register paths from post-route timing reports
- Replace the flip-flops at the path endpoints with ETFF cells via ECO commands
- Re-run place-and-route, and repeat until timing stops improving
The ETFF was modeled as a custom standard cell: a .lef with doubled area and a .lib with modified timing, where the setup time is lowered by the transparency window width to allow late data, and the hold time is increased to prevent the next signal from passing through. After insertion, ETFF instances are marked non-modifiable and the cell is excluded from general optimization, so the tool cannot silently add or swap ETFFs on its own.
The whole methodology was automated with Python scripts that clone and configure the flow (libraries, plug scripts, make targets), generate the ECO insertion script from the lowest-slack paths report, and run the baseline plus all iterations. Setting the ETFF budget and iteration count is all that is needed to launch a full experiment.
Results
The flow was validated on the course-provided DA2 ‘BlaBla’ design with a 200 ps time-borrowing window, comparing two insertion budgets. Starting from a baseline that standard optimization could not close, iterative ETFF insertion reached positive slack: by iteration 4 with 320 ETFFs, and by iteration 6 with 200 ETFFs.
Worst Negative Slack across iterations (200 ps ETFF window)
| Iteration | WNS, 200 ETFFs [ps] | WNS, 320 ETFFs [ps] |
|---|---|---|
| 0 (baseline) | 5.288 | 5.288 |
| 2 | 3.962 | 0.502 |
| 3 | 21.332 | 10.712 |
| 4 | 7.001 | 0 (positive slack) |
| 5 | 20.483 | - |
| 6 | 0 (positive slack) | - |
PPA summary for the converged configurations
| Configuration | Power | Performance | Area |
|---|---|---|---|
| 200 ETFFs | 11.32 mW | 1.11 GHz | 31,256 µm² |
| 320 ETFFs | 11.47 mW | 1.11 GHz | 31,462 µm² |
The larger budget closes timing in fewer iterations at a small cost in power and area.
The layout views below show the physical progression: the first iteration inserts 10 ETFFs (highlighted in blue) targeting near-critical paths, while the final converged design has 196 ETFFs distributed across the core to mask all remaining setup violations.
One practical observation was oscillatory WNS behavior across iterations: paths that improve after ETFF insertion drop out of the selection in the next iteration, then reappear as critical after re-optimization. A monotonic insertion schedule that accumulates ETFFs across iterations, starting with a larger set and adding smaller increments while keeping prior placements fixed, could reduce these oscillations and accelerate convergence.
Limitations and Open Challenges
- The cell's area and timing properties are estimates, and the error-signal net is not generated. In a real deployment that error signal would drive adaptive voltage and frequency control.
- ETFFs on consecutive pipeline stages interact across clock boundaries: an upstream ETFF that borrows time erodes the downstream stage's margin in the next cycle, which breaks the path-based separation assumed by static timing analysis.
- Fundamentally, if the clock frequency is scaled up during long periods without late signals, a critical path that eventually toggles could arrive after the detection window has passed, so guaranteeing detection of all violations may require reintroducing part of the margins the technique sets out to eliminate.